1. Introduction
2. What is a Root of Trust?
3. Why open silicon: OpenTitan and Pavona
4. Threats and trust boundaries
6. The simulated chip
7. 1. Booting a chip on your laptop
   1. 1.1. Development environment
   2. 1.2. Building Egret in Verilator
   3. 1.3. Hello, World!
   4. 1.4. Reading the memory map
9. Secure boot
10. 2. How a chip trusts its own code
    1. 2.1. The chain of trust
    2. 2.2. Signing and verifying an image
    3. 2.3. Building and running a signed chain
    4. 2.4. ePMP memory protection
    5. 2.5. Reading the boot log
12. Secure storage and lifecycle
13. 3. Keeping secrets and managing state
    1. 3.1. OTP and flash scrambling
    2. 3.2. Lifecycle states
    3. 3.3. The lifecycle gate
15. Identity and keys (DICE)
16. 4. Where a chip's identity comes from
    1. 4.1. The OTP root secret
    2. 4.2. Key manager derivation and DICE
    3. 4.3. Software binding and key versioning
18. Attestation
19. 5. Proving who you are
    1. 5.1. Creator and Owner Identity Certificates
    2. 5.2. The certificate chain
    3. 5.3. Verifying a chain off-device
21. Post-quantum crypto
22. 6. Cryptography that survives quantum computers
    1. 6.1. The acc coprocessor
    2. 6.2. ML-KEM, ML-DSA, and SPHINCS+
    3. 6.3. NIST known-answer tests
    4. 6.4. PQC-enabled secure boot
24. Provisioning and ownership
25. 7. Birth and handover of a device
    1. 7.1. Personalization
    2. 7.2. ECIES-wrapped secret injection
    3. 7.3. Ownership transfer
27. Egret as a secure co-processor
28. 8. Driving the root of trust from a host
    1. 8.1. The command channel
    2. 8.2. One command, end to end
    3. 8.3. Building a real host
    4. 8.4. Breaking the link
31. 9. References